Main Reference PaperDistributed Packet Buffers for High-Bandwidth Switches and Routers, IEEE Transactions on Parallel and Distributed Systems, July 2012.
  • Large memory requirement and high time complexity affects the property of high speed routers with short response time with the support of multiple queues. A load balancing algorithm is proposed with the design of scalable packet buffer having minimized overhead by coordinating multiple subsystems

+ Description
  • Large memory requirement and high time complexity affects the property of high speed routers with short response time with the support of multiple queues. A load balancing algorithm is proposed with the design of scalable packet buffer having minimized overhead by coordinating multiple subsystems

  • To increase the throughput and storage capacity of the buffer using parallel mechanism

  • To propose a novel packet buffer architecture for reducing the response time

+ Aim & Objectives
  • To increase the throughput and storage capacity of the buffer using parallel mechanism

  • To propose a novel packet buffer architecture for reducing the response time

  • Effective buffer usage technique is integrated with the architecture on the basis of current network traffic

+ Contribution
  • Effective buffer usage technique is integrated with the architecture on the basis of current network traffic

  • OS : Window 7 (Cygwin) / Ubuntu 12.04 LTS 64bit.

  • Simulator: NS 2.35, Language : TCL and AWK script, (C++)

+ Software Tools & Technologies
  • OS : Window 7 (Cygwin) / Ubuntu 12.04 LTS 64bit.

  • Simulator: NS 2.35, Language : TCL and AWK script, (C++)

  • B.E / B.Tech / M.E / M.Tech

+ Project Recommended For
  • B.E / B.Tech / M.E / M.Tech

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