Research Area: Internet of Things
Data communication stack on Internet of Things (IoT)-devices is traditionally implemented in software as a part of their operating systems. In IoT-applications for which resource constrained IoT-devices are deployed, leveraging microprocessor(s) for both computing and data communication tasks may result in poor application performance and high power consumption. In order to alleviate these performance and power issues, using System on Chip (SoC) field programmable gate arrays (FPGAs) for the hardware acceleration of the performance- or power-critical software tasks is a recent, popular trend in the literature. On the other hand, constrained application protocol (CoAP) is a pivotal network protocol for many IoT-applications. Motivated by these facts, in this article, a hardware accelerator for a CoAP server network stack is proposed and realized on a SmartFusion2 SoC FPGA. The hardware accelerated CoAP server network stack is thoroughly evaluated and compared in terms of its performance, latency, power consumption, and FPGA resource utilization against a baseline software implemented CoAP server network stack. The evaluation results obtained clearly show that the CoAP hardware accelerator provides significantly higher performance and lower response message latency, while consuming significantly less power. Consequently, the CoAP hardware accelerator proposed seems to be a strong viable solution for the resource constrained IoT-devices.
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Author(s) Name: Burak Batmaz; Atakan Dogan
Journal name: IEEE Internet of Things Journal
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Publisher name: IEEE
DOI: 10.1109/JIOT.2021.3083196
Volume Information: Volume: 8, Issue: 24, Page(s): 17790 - 17801
